This invention relates to a current limit circuit for providing automatic protection of a power transistor or the like from damage caused by excessive currents flowing therein as a result of an overload condition, such as a short-circuit at the load. More particularly, the invention relates to a current limit circuit adapted to protect the power semiconductor device in a so-called "high side" Intelligent Power Switch (IPS or "smart power" switch).
A "smart power" device or intelligent power switch is an integrated circuit in which control functions are provided by low voltage logic devices integrated along side of power semiconductor devices, such as power MOSFETs, together on a common chip. It is customary in known high side power chips to isolate the integrated low power components from the high power components on the chip by the provision of special diffusions or barrier layers of differing conductivity types or by the provision of dielectric layers.
The invention is particularly useful in automotive applications, but is not limited to this field of technology. In recent years there has been a dramatic increase in the use of semiconductor electronic systems in the automobile, such as in ignition/fuel control, switches for headlamps, monitoring of emissions and braking systems. All of these control functions require safe and reliable semiconductor devices for monitoring, logic and power control. A key component for these various automotive applications is an inexpensive and reliable intelligent power switch (IPS) that is able to drive high current loads (for example, up to 10 A) such as headlights, solenoids and small electric motors. The IPS must be able to withstand a supply voltage of up to 60 volts and at the same time provide self protection against short circuits and excessive temperatures.
A typical IPS device in an automotive electronics system requires an integrated circuit chip which combines 60 volt power components and both low voltage (5 V to 12 V) and high voltage (60 V-80 V) logic components. A typical chip must have the intelligence to protect the switch against various potentially destructive conditions such as a short circuit to ground, a reverse battery and voltage surges due to inductive loads. The intelligent power switch device should also provide thermal shut down, rail-to-rail current limiting and should detect open load and over voltage conditions and provide an indication of any overload condition. The provision of these supervisory and safety features is complicated because of the wide variation of supply voltages, for example, from approximately 6 V to 60 V, and the varied nature of the fault conditions which may occur.
A typical IPS chip consists of four main functional blocks, a gate control unit, a sensor block, a control logic and a power supply. In the case of a high side power switch, the gate control unit provides gate drive to the power switch by means of an oscillator/charge pump circuit. The sensor block contains voltage, current and temperature detectors in order to accurately monitor the condition of the intelligent power switch chip and the load. The control logic block diagnoses potential fault conditions and initiates the necessary corrective action. The power supply block contains precision analog circuits, such as a band-gap reference, so as to provide the necessary reference and bias voltages and currents for the chip. The total supply current flows to ground via a reverse-battery protection circuit.
Various techniques have been proposed for limiting the current through a power transistor. One known circuit for providing current limit protection for a high side intelligent power switch is shown in FIG. 1 of the drawing. In this circuit a power switch 1, for example a power MOSFET element, is connected in series with a load resistor 2 between one terminal of a battery and ground. A second series circuit consisting of a sense MOSFET 3 and a sense resistor (R.sub.S) 4 is connected between the battery terminal and a junction point 5 between the power MOS switch 1 and the load 2. An NMOS FET 6 is connected between the gate of the power MOS transistor 1 and the junction point 5. The gate of pull-down transistor 6 is connected to a junction point between the field effect transistor 3 and the sense resistor 4. The gates of the field effect transistors 1 and 3 are connected in common to a gate drive input terminal 7. A serious disadvantage of this current limiting scheme is the fact that the current limit value is determined essentially by the threshold voltage of the NMOS transistor 6, which voltage is subject to a wide variation due to variations in the manufacturing process of the IPS chip. In addition, a typical value of the threshold voltage (V.sub.th) is 1 V or more and this value produces too high a voltage drop across the sampling sense resistor 4 to provide accurate current mirroring between the field effect transistors 1 and 3.
A known variation of the FIG. 1 current limiting power switch circuit includes a comparator connected between the junction point of sense FET 3 and sense resistor 4 and the gate of the pull-down NMOS transistor 6. In this variation, a first input of the comparator is connected to the aforesaid junction point, a second input is connected to a source of reference voltage, and its output is connected to the gate of the NMOS field effect transistor 6. A compensation capacitor of the order of 100-150 pF is connected between the comparator output and the drain of the NMOS transistor 6 in order to provide stability. The compensation capacitor is required because the load capacitance to be driven and formed by the gate capacitance of the power MOSFET 1 is very large. This current limit circuit is therefore unattractive because of the chip area requirements and the stability problem.